Study and Analysis of Universal Gates Using Stacking Low Power Technique
نویسندگان
چکیده
The main objective of this paper is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, this work focuses on the reduction of the power dissipation, which is showing an ever-increasing growth with the scaling down of the technologies. Various techniques at the different levels of the design process have been implemented to reduce the power dissipation at the circuit, architectural and system level. Conventional NAND gate and Nor gate are designed snd then compared with the stack NAND and stack NOR using 180nm technology.
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